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| Highlights |
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- 40 MHz bandwidth
- Double 10 bit data
- 2.5 MHz sampling frequency
- 8Kword x 32 channel memory event buffer
- BLT32/MBLT64/CBLT32/CBLT64 data transfer
- Multicast commands
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The CAEN Model V789 ICARUS digital board is a 32-channel digitizer readout board specially designed for the ICARUS experiment. This board is the evolution of a prototype (ARIANNA board). This board is housed in a 1-unit wide VME module and its function is to read the digital data coming from the Model V791 (ICARUS analog board) and to store them in a Multi Event Buffer (MEB) memory, according to a complex, programmable trigger logic.
The digital data are transferred to the module via a fast link (21-bit word, 40 MHz frequency). Each word contains two ADC-data (10 bit + 10 bit) and a SYNC signal (1 bit). The two ADC-data refer to two 16-channel groups that have been multiplexed temporally, whereas the SYNC signal tags the channel 0 of each 16-channel group. In the whole, the module takes 400 ns to read out the 32 channels.
In order to allow the test of the module also without the link, some test patterns are stored in a relevant FIFO memory. These test patterns, thus, can substitute the input data from the external ADCs.
Each 16-channel group can be seen as an independent unit: only the absolute time counter, the test pattern FIFO memory and the VME interface are common to both the groups.
The digital data are stored in a static RAM divided into a programmable number of Circular Buffers. The write access to the buffers is controlled by the trigger logic, which is sensitive to the PEAK signals generated by two DAEDALUS chips [1,2], one for each 16-channel group. In particular, each DAEDALUS chip can be seen as constituted by four independent units, each of which controls 4 channels. The detection of a PEAK on one of the channels causes the following:
1) the data in the presently pointed buffer are frozen,
2) the buffer is enabled to be read out via VME,
3) a set of external triggers are generated.
If other buffers are ready to be written on, the data acquisition continues in the following buffer. This operation can occur also as a consequence of specific external triggers. A parallel task provides to store useful information concerning the event (absolute time tag, trigger specifications, etc.) in the Header FIFO.
The RAM memory which contains the samples of the stored waveform can be accessed via VME, as well as the FIFO memory. Both the buffer and trigger controls are programmable via VME.
Each DAEDALUS chip is located on a piggy-back board in order to allow possible test procedures independently from the V789 module.
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| Package |
1-unit wide, 6-unit VME Module; P1 and P2 connectors |
| Number of channels |
32 channels divided into two independent blocks (block A = ch[15:0], block B = ch[31:16] |
| Input samples |
10 bit double data, 40 MHz (16+16 channels multiplexed in time) |
| Sample Rate |
2.5 MHz |
| Absolute time |
32 bit counter at 25 MHz (in the whole about 172 sec) |
| Trigger sources |
Peak detection, Left/Right Trigger, GLOBAL Trigger, EXT Trigger, VME Trigger |
| Memory |
Multi Event Buffer. 8Kword per channel, to be divided into buffers with programmable dimensions from 64 to 4096 words |
| Test Pattern |
10 bit, 1Kword (common to all the 32 channels) |
| VME |
Registers: Single Access, A32, D16 mode.
Output Buffer: Single Access or BLT access in A32, D32 mode.
Interrupter with fixed priority.
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| Code |
Description |
| WV789XAAAAAA |
V789 - ICARUS Read-out Board |
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| © 2000 - 2010 CAEN S.p.A. All rights reserved. |
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