 Support - Glossary |
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ADC Conversion Time |
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The time required, after the sample command, to digitize the analog signal
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ADC Dead Time |
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The minimum amount of time required after the end of a GATE to have the ADC ready for a new acquisition
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ADC Resolution |
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The number of bits in which the ADC full scale range is divided
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Address Modifier |
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It is the code which carries the information about the size and the type of VME data transfer
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Analog Adder |
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A linear Fan-In
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AND |
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Logical designation or circuit function meaning that all inputs must be in the TRUE state for a TRUE output
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Anti-Coincidence |
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An input signal which suppresses the normal functioning of the unit for the duration of its application
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Backplane |
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A monolitic, multilayer printed circuit board at the rear of a crate providing bus dataway, power lines and modules’ connectors
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Bandwidth |
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The frequency range over which the gain of an amplifier or other circuit does not vary by more than 3 dB
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Baseline Restorer |
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A circuit that maintains the amplifier DC output (baseline) at fixed potential independently from counting rate
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Baseline Shift |
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Drift of the amplifier DC level (baseline) that may impair the peak amplitude stability
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Block Transfer (BLT32) |
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A 32 bit VME data transfer from/to a series of adjacent locations of a module
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Bridged Outputs |
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Parallel output connections which share the same driver
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CAMAC |
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Computer Automated Measurement And Control; international standard of modular instrumentation defined by the ESONE Committee of the JNRC (document EUR4100e, 1969 and subsequent revisions);
CAMAC One single-width unit, as per IEEE Standard 583, has 305 mm x 182.9 mm x 17 mm overall dimensions.
They can, however, also be built in multiples of this standard, that is, double-width, triple-width etc.
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CANbus |
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Controlled Area Network; network consisting of multiple microcontrollers that need to communicate with each other
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Chained Block Transfer CBLT |
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Sequential read out of multiple VME slave modules selected by a single address cycle
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Charge ADC |
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An ADC which measures the input charge integrated during the GATE period
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Charge Sensitive Preamplifier |
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A preamplifier whose peak output amplitude is directly proportional to the input integrated charge
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Coincidence Unit |
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A device which performs the AND logic function of two or more inputs
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Common Mode Range |
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The maximum range (usually voltage) within which differential inputs can operate without a loss of accuracy
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Common Mode Rejection Ratio |
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The ratio between the common mode input noise and the output voltage, expressed in dB. It expresses the ability to reject the common mode noise
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Common Mode Noise |
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The noise which appears equally, and in phase, on the IN+ and IN- nodes of a differential input with respect to ground
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Common Start |
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A signal common to all input ch. which marks the beginning of a time interval measurement in a TDC
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Common Stop |
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A signal common to all input ch. which marks the end of a time interval measurement in a TDC
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Complementary Output |
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A logical signal with its FALSE state and TRUE state reversed from that of the normal output signal
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Constant Fraction Discriminator |
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A discriminator which allows to minimize time walk errors encountered triggering constant rise time and varying amplitude signals
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Control and Status Register (CSR Space) |
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A register used to control the operation of a device and/or record the status of an operation. Its allocation and usage is part of the VME specification
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Crosstalk |
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Unwanted coupling of a signal from one channel to another one
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