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32+2 Channel 12bit 5 GS/s Digitizer |
Coming Soon |
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| Tentative Data |
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- 32+2 channel
- 12 bit 5 GS/s Switched capacitor ADC
- 1 Vpp input dynamics, single ended, 50 Ohm, MCX coaxial connectors
- Based on DRS4 chip (Paul Scherrer Institute design)
- 1024 storage cells per channels (200 ns recorded time per event @ 5GSample/s)
- Trigger Time stamps
- Memory buffer: 128 events/ch (optional: 1024 events/ch)
- ~33 μs conversion time
- Possibility of FPGA for real-time data processing (for example Zero Suppression and Data Reduction algorithms)
- VME64X-compliant and Optical Link interfaces
- PCI controller available for handling up to 8 Modules daisy chained via Optical Link
- Firmware upgradeable via VME/Optical Link
- Libraries (C and LabView), Demos and Software tools for Windows and Linux
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Overview |
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The Mod. VX1742 is a VME64X 6U module housing a 32+2 Channel 12 bit 5 GS/s Switched-Capacitor Digitizer with 1 Vpp INPUT dynamic range on single ended MCX coaxial connectors
The DC offset adjustment (range ± 0.5V) on each channel by 16bit DACs allows a right sampling of a bipolar (Vin=± 0.5V) up to a full positive (Vin= 0 ÷ +1V) or negative (Vin= 0 ÷ -1V) analog input swing without losing dynamic resolution.
The modules features a front panel Clock-In and a PLL for clock synthesis from internal/external references.
The input signals are continuously sampled (up to 5 GHz frequency) in a circular analog memory buffer (1024 cells of 150 fF capacitors). The arrival of a trigger signal freezes the currently stored signal in the sampling capacitors. The signal is then read out via a read shift register for external digitization.
The analog samples in the DRS chips are rapidly (30 ns /sample) digitized by 12 bits ADC and stored in a digital memory buffer (dual port multi event buffer able to store 128 event/ch).
The readout (from VME or Optical link) of a frozen event is independent from the write operations of successive events.
The 2 additional channels can be used to digitize external master clock for applications where high resolution timing (up to 200 ps) is required for many DRS4 chips (The board is divided into 2 sections containing both 2 DRS4 chips)-
Mod.VX1742 supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source t. When synchronized, all data will be aligned and coherent across multiple VX1742 boards.
The trigger signal can be provided via the front panel input as well as via the VMEbus.
The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer (D32), 32/64 bit Block Transfer (BLT, MBLT, 2eVME, 2eSST) and 32/64 bit Chained Block Transfer (CBLT).
The board houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it is possible to connect up to eight ADC boards (256+16 ADC channels) to a single Optical Link Controller (Mod. A2818). Optical Link and VME access are internally arbitrated.
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