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The Mod. V1761 is a 1-unit wide VME 6U module housing a 2 Channel 10 bit 4 GS/s Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities.
Input dynamics is 1 Vpp (single ended or differential).
The DC offset of the input signal can be adjusted channel per channel by a programmable 16bit DAC on single ended input version.
The modules feature a front panel clock/reference In/Out and a PLL for clock synthesis from internal/external references. This allows multi board phase synchronizations to an external clock reference or to a clock Digitizer master board.
The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either via VME or via Optical Link. The acquisition can continue without dead time in a new buffer.
Each channel has a SRAM memory buffer (available in the 7.2 and 57.6 MSamples/ch sizes), with independent read-write access divided in 1 to 1024 buffers of programmable size.
The trigger signal can be provided via the front panel input as well as via the VMEbus, but it can also be generated internally. The trigger from one board can be propagated to the other boards through the front panel Trigger Output.
An Analog Output allows to reproduce the sum of the input signals as well as the majority of the buffer occupancy.
The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer (D32), 32/64 bit Block Transfer (BLT, MBLT, 2eVME, 2eSST) and 32/64 bit Chained Block Transfer (CBLT).
The boards houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it is possible to connect up to eight ADC boards (64 ADC channels) to a single Optical Link Controller (Mod. A2818). Optical Link and VME access are internally arbitrated.
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