 R&D - Articles |
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| A PORTABLE INTELLIGENT ECG MONITOR BASED ON WIRELESS INTERNET AND EMBEDDED SYSTEM TECHNOLOGY |
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Abstract
In this article, we present a Portable Intelligent ECG Monitor (PIEM) which can be used in a Wireless Remote Monitoring System. For the hardware design, Advanced RISC Machines (ARM) as well as ECG Application Specific Integrated Circuit (ASIC), GSM/GPRS and NAND Flash technologies is adopted. As for the software implementation, a real-time kernel called μC/OS-II and some related application programs were developed, among which an efficient and robust on-line ECG interpretation algorithm is included. A prototype of this device is finally accomplished and has been put into use in the clinical environment for one month. The results of the experiment show that this PIEM is clinically approved, accurate in its measurement, highly mobile, easy-touse, durable and light-weight. Once this prototype is developed into product, there's no doubt that more and more cardiac patients will benefit from it.
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| GRAAL: A TOOL TO DESIGN HIGHLY DEPENDABLE SRAM ARCHITECTURE FOR AEROSPACE APPLICATIONS |
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Abstract
The scientific space missions require high-speed and low-power on-board data storage capabilities that are obtained with cheap and non qualified Components Off The Shelf (COTS) memories, in which a change in the stored data can unfortunately occur because of the radiation effects. This paper presents an implementation tool (GRAAL) to design a high-reliability memory architecture that consists in a wrapper placed around the target memory. The memory collar together with the target memory behave like a Dependable Memory Core that can be embedded in complex systems.
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| GRAAL: a Tool for Highly Dependable SRAMs Generation |
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Abstract
Commercial tools for the automatic insertion of testing structures so far cover the generation of highly dependable SRAMs only partially. This paper presents a tool to achieve proper reliability levels in systems based on memories. The tool allows the automatic insertion of BIST architectures for both OFF-line and ON-line memory testing. The set of algorithms and architectures supported by the tool is not limited, but it can be easily extended, to include innovative architectures and achieve the reli-ability requirements in any application. Using the tool, the user can generate dependable memories trading-off in the de-sign process the dependability properties and costs.
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| A 12-bit pipelined self-calibrated radiation hardened ADC for aerospace applications |
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Abstract
A front-end ASIC chip designed to collect signals from CCD or CMOS photodetectors allows the realization of a compact and low-power data acquisition system performing analogue processing and digitalization. The device has been fabricated in Rad-Hard technology and several design solutions have been used, both in the digital and in the analogue section, to improve the performance and to reduce the susceptibility to single event effects. The paper describes the chip design and the experimental characterization of the prototypes before and after radiation tests.
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| RAD-HARD ASIC FOR PHOTODETECTOR SIGNAL PROCESSING |
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Abstract
A front-end ASIC designed to collect signals from CCD or CMOS photodetectors allows the realization of a compact and low-power data acquisition system, performing analogue processing and digitization. In the design of the device, fabricated using a Rad-Hard technology, several solutions have been used, both in the digital and in the analogue section, to improve the performance and to reduce the susceptibility to single event effects. The paper describes the chip design and the experimental characterization of the prototypes before and after radiation tests.
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| An ultra low power switched opamp-based 10-B integrated ADC for implantable biomedical applications. |
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Abstract
These papers describe an ultralow power switched opamp-based integrated ADC for biomedical signal processing, in particular coming from cardiac pacemakers. The ADC consumption, measured on 10 chip samples and averaged, is 8.18 µW (stand-by value: 1 nW) for the analog part and of 9.71 µW (5 nW) for the digital one, using a supply battery of 2.8 V. The converter has a resolution of 10-b, its typical operating clock frequency is 32 KHz (2.9 KS/s sampling rate) and is able to reach the same resolution at 2V (0.7 KS/s sampling rate), with a dissipation of 1 µW and 1.3 µW for analog and digital part, respectively.
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| INTEGRATED DEVELOPMENT TOOLS SUITE FOR THE SPACEWIRE RTC ASIC |
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Abstract
The SpaceWire RTC device is a fully integrated LEON2-FT based System on Chip that among other features, provides the capability to bridge traffic between the SpW network and the CAN bus. The SpW RTC Development Suite is the collection of HW/SW components designed to stimulate all the RTC interfaces and to drive all its communication links.
In this paper a brief description of the RTC ASIC and the Development Suite Tool are presented before focusing on the SpaceWire aspects of the two devices and their test chain.
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CARDIC - Multiparameter Medical Acquisition Integrated System |
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> more |
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IPPM - Integrated Payload Processing Module |
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> more |
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RESEDA.pdf
